Multi-layer gate stack

ABSTRACT

A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF 4  and CHF 3  at a pressure of at least 10 mtorr.

BACKGROUND

[0001] Modern integrated circuits are constructed with up to severalmillion active devices, such as transistors and capacitors, formed inand on a semiconductor substrate. Interconnections between the activedevices are created by providing a plurality of conductiveinterconnection layers, such as polycrystalline silicon and metal, whichare etched to form conductors for carrying signals. The conductivelayers and interlayer dielectrics are deposited on the silicon substratewafer in succession, with each layer being, for example, on the order of1 micron in thickness.

[0002] A gate structure is an element of a transistor. FIG. 1illustrates an example of a gate stack 8. A semiconductor substrate 10supports a gate insulating layer 16, which overlaps doped regions(source/drain regions) in the substrate (12 and 14), and the gateinsulating layer supports a gate 18, which is typically polycrystallinesilicon. On the gate is a metallic layer 30. The metallic layer may beseparated from the gate by one or more other layers, such as nitrides,oxides, or silicides, illustrated collectively as barrier layer 20. Themetallic layer may in turn support one or more other layers(collectively 40), such as nitrides, oxides, or silicides. Oxide 22 maybe formed on the sides of the gate to protect the gate oxide at the footof the gate stack; and insulating spacers 24 may be formed on eitherside of the gate stack. Furthermore, contacts to the source/drainregions in the substrate, and to the gate structure, may be formed.

[0003] Self-aligned contacts (SAC) allow the design of a semiconductordevice to have a distance between the gate and the via contact to thesubstrate, to be at most one-half the minimum gate width. Typically, SACuses a nitride layer on the gate stack, together with spacers thatinclude nitride, to prevent a misaligned contact from contacting thegate itself. If the nitride were not present, then the etch used to formthe hole which will become the contact would pass through the dielectriclayer all the way to the gate. When present, the nitride layer andspacers acts as an etch stop, preventing misalignment from forming ahole all the way to the gate, and therefore allowing design of thedevice to have a much smaller average distance between the contact andthe gate.

[0004] The nitride layer on the gate stack has at least a thickness of800 angstroms when used for forming SAC. If used only for otherpurposes, such as an etch-stop layer or a hard mask, a thickness of lessthan 800 angstroms is used. Also, the thickness of at least 800angstroms is the thickness after the dielectric layer has been formed;the nitride layer is usually thicker when originally formed, allowingfor a loss of about 500 angstroms during the gate etch (i.e. thicknessfor the hard mask function), and a loss of about 200 angstroms duringnitride spacer formation.

[0005] There is an ongoing need to reduce the size of the elementswithin integrated circuits and semiconductor structures. As the size ofan element is reduced, shorter wavelength radiation is need to forexposing the photoresist in order to obtain the smaller featuresdesired. Consequently, photoresists sensitive to the shorter wavelengthradiation must also be used. In order to obtain features on the order of0.1 micron, radiation having a wavelength of 193 nm is used, and thephotoresists sensitive to this wavelength are referred to as 193 nmresists. A variety of these resists are commercially available, such asT9269 (from Clariant International, Ltd., Muttenz, Switzerland), 6A100(Tokyo Ohka Kogyo, Kawasaki-shi, Japan), and AR414 and AR237 (both fromJapan Synthetic Rubber Co., Ltd., Tokyo, Japan).

[0006] An undesirable problem that arises, however, is that the etchingprocesses have been optimized for the specific photoresists, andswitching to different photoresists along with a reduction is scale, canresult in problems, such as an increase in line-edge roughness (see “AnExperimentally Validated Analytical Model For Gate Line-Edge Roughness(LER) Effects on Technology Scaling” Diaz, C. H., et al., IEEEElectronic Device Letters, Vol. 22, No. 6, pp. 287-89 (June 2001)).Increased line-edge roughness will result in device deficiencies, and areduction in device yield.

BRIEF SUMMARY

[0007] In a first aspect, the present invention is a method of making asemiconductor structure, comprising etching a nitride layer with aplasma to form a patterned nitride layer. The nitride layer is on asemiconductor substrate, a photoresist layer is on the nitride layer,and the plasma is prepared from a gas mixture comprising CF₄ and CHF₃ ata pressure of at least 10 mtorr.

[0008] In a second aspect, the present invention is a method of making asemiconductor structure, comprising etching a nitride layer with aplasma to form a patterned nitride layer. The nitride layer is on astack, the stack is on a semiconductor substrate, and the stackcomprises (i) a gate layer, comprising silicon, and (ii) a metalliclayer, on the gate layer. A photoresist layer is on the nitride layer,the photoresist layer comprises a 193 nm photoresist, the patternednitride layer has a line-edge roughness of at most 8 nm, and the plasmacomprises carbon, hydrogen and fluorine.

[0009] In a third aspect, the present invention is a semiconductorstructure, comprising a patterned nitride layer on a semiconductorsubstrate. The patterned nitride layer has a line-edge roughness of atmost 9 nm, and an isolation region of the substrate has a width of atmost 0.4 microns.

[0010] Line-edge roughness is defined as 3σ of ten critical dimension(CD) readings taken uniformly at steps of 1 micron along a given line(see the description of long-range LER in “An Experimentally ValidatedAnalytical Model For Gate Line-Edge Roughness (LER) Effects onTechnology Scaling” Diaz, C. H., et al., IEEE Electronic Device Letters,Vol. 22, No. 6, pp. 287-89 (June 2001)).

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 shows a gate stack structure.

[0012] FIGS. 2-8 illustrate a method of forming the structure of FIG. 9.

[0013]FIG. 9 shows a gate stack of the present invention.

[0014]FIG. 10 show the gate stack of FIG. 9 after further processing.

DETAILED DESCRIPTION

[0015] The present invention makes use of the discovery of a new nitrideetching process to produce a line-edge roughness of at most 9 nm.Typically, nitride etching will result in a line edge roughness of 10-12nm for a 193 nm resist, when etching is carried out with a plasmaprepared from CH₂F₂, at a pressure of 4 mTorr. A line-edge roughness ofat most 9 nm is achieved by significantly increasing the pressure of theetching plasma, and increasing the concentration of fluorine in theplasma.

[0016] Referring to FIG. 2, a gate insulating layer 102 is on asemiconductor substrate 100. The semiconductor substrate may be aconventionally known semiconductor material. Examples of semiconductormaterials include silicon, gallium arsenide, germanium, gallium nitride,aluminum phosphide, and alloys such as Si_(1-x)Ge_(x) andAl_(x)Ga_(1-x)As, where 0≦x≦1. Preferably, the semiconductor substrateis silicon, which may be doped or undoped. The gate insulating layer 102may be a conventionally known insulating material. For example, the gateinsulating layer may contain silicon oxide or silicon oxynitride.

[0017] Referring to FIG. 3, a gate layer 105 may be formed on the gateinsulating layer. The gate layer may contain a variety of semiconductingmaterials. Typically, a gate layer contains polycrystalline silicon(poly) or amorphous silicon. The gate layer may be doped with one typeof dopant (P⁺ or N⁺), or it may contain both types of dopants indiscrete regions. A split gate is a gate layer containing both P⁺ and N⁺doping regions.

[0018] In the case of a split gate, those regions of the gate that areP⁺ doped (such as with B or BF₂+) are over N⁻ doped channel regions ofthe substrate, forming a PMOS device; those regions of the gate that areN⁺ doped (such as with As⁺ or phosphorus⁺) are over P⁻ doped channelregions of the substrate, forming an NMOS device. The P⁺ and N⁺ dopingregions of the gate are separated by a region which is on an isolationregion of the substrate; this isolation region has a width of at most0.4 microns, more preferably at most 0.36 microns. The doping of theregions of the gate is preferably carried out after forming the gate, bymasking and doping each region separately, or by an overall doping ofthe gate with one dopant type, and then masking and doping only oneregion with the other dopant type (counter doping).

[0019] Referring to FIG. 4, a barrier layer 115 may optionally be formedon the gate layer. The optional barrier layer may contain a variety ofmaterials, including nitrides, silicides, and oxides, and is preferablya conductive material. For example, the barrier layer may containrefractory suicides and nitrides. Preferably, the barrier layer containssilicon nitride, or a nitride or silicide of a metal such as tantalum,titanium, niobium or tungsten, for example tungsten nitride.

[0020] Referring still to FIG. 4, a metallic layer 125 may be formed onthe gate layer, or the barrier layer 115, if it is present. Preferably,the metallic layer has a thickness of 200-600 angstroms, more preferably300-500 angstroms, most preferably 325-450 angstroms. The metallic layer125 may contain a variety of metal-containing materials. For example, ametallic layer may contain aluminum, copper, tantalum, titanium,tungsten, or alloys or compounds thereof. Preferably, the metallic layercomprises tungsten or titanium. The metallic layer may be formed, forexample, by physical vapor deposition (PVD) of the metal, or by lowpressure chemical vapor deposition (LPCVD) of a mixture of a metalhalide and hydrogen.

[0021] Referring to FIG. 5, a barrier layer 135 may optionally be formedon the metallic layer. The formation of the second optional barrierlayer may be performed as described for the first optional barrier layer115, and this layer may be formed of the same materials, and to the samethicknesses.

[0022] Referring still to FIG. 5, an etch-stop layer 145 may be formedon the metallic layer by a variety of methods, including chemical vapordeposition (CVD). Preferably, the etch-stop layer is a nitride layer.More preferably, the etch-stop layer is silicon nitride formed by PECVD.The etch-stop layer may vary in composition, so that the top of theetch-stop layer is anti-reflective, for example so that the top of theetch-stop layer is silicon rich silicon nitride, or silicon oxynitride;this layer may also act as a hard mask to protect the etch-stop layerduring subsequent etches. Alternatively, a separate anti-reflectivelayer (ARC) may be formed.

[0023] Preferably, the etch-stop layer is formed rapidly at a relativelylow temperature. For example, if the gate layer contains both P⁺ and N⁺doping regions, diffusion of the dopants may occur if the wafer ismaintained at sufficiently high temperatures for a prolonged period oftime. Thus, it is desirable that any high temperature processing isperformed only for relatively short periods of time. Likewise, it isdesirable that any lengthy processing is carried out at relatively lowtemperatures. Preferably, the etch-stop layer is formed at a temperatureof at most 750° C., if the atmosphere is substantially devoid of oxygen,or in a reducing environment (hydrogen rich). Under typical conditions,a temperature of at most 600° C. is preferred, at most 450° C. is morepreferred. A temperature of at least 350° C. is preferred, such as 400°C. The depositing of the etch-stop layer is preferably carried out at atemperature and for a time that does not result in substantial diffusionbetween the P⁺ region and the N⁺ region in a split gate.

[0024] Preferably, the etch-stop layer has a thickness of at least 800angstroms, more preferably a thickness of at least 1100 angstroms, mostpreferably a thickness of at least 1200, after etching of the gatelayer, and after formation of gate spacers. About 500 angstroms ofetch-stop may be lost during the gate layer etch, and about 200angstroms of etch-stop may be lost during the spacer formation.Preferably, at least 1500 angstroms thickness of etch-stop aredeposited, more preferably at least 1800 angstroms thickness ofetch-stop are deposited, most preferably 2100 angstroms thickness ofetch-stop are deposited. Preferably, after the gate layer etch and afterspacer formation (or, alternatively, after the dielectric layer isformed), the etch-stop layer has a thickness of 800-1800 angstroms, morepreferably a thickness of 1100-1500 angstroms, most preferably athickness of 1200-1400 angstroms. Similarly, the thickness depositedwould preferably be these same ranges, with an additional 700 angstromsadded to accommodate loss during the gate layer etch and spacerformation, when material are used which may result in a loss of theetch-stop layer at these points in the process.

[0025] Referring to FIGS. 6-9, each layer may be patterned to form thegate stack. The patterning may be accomplished, for example, byconventional photolithographic and etching techniques. Referring toFIGS. 6 and 7, the etch-stop layer may be etched to form a patternedetch-stop layer 150, for example by forming a patterned photoresist 210on etch-stop layer 145 (FIG. 6) and then etching the exposed portions ofthe layer. A hydrofluoric acid dip may be used to remove sidewallpassivation.

[0026] The etch-stop etching may be carried out by exposure to a plasmaformed from a mixture of gasses. Preferably, the gasses and plasmacomprise carbon, fluorine and hydrogen. Preferably, the atomic ratio offluorine: hydrogen is 43:1 to 13:3, more preferably 35:1 to 5:1, mostpreferably 27:1 to 7:1. Preferably, the mixture of gasses includes CF₄and CHF₃; preferably the ratio by volume of CF₄: CHF₃ is 10:1 to 1:3,more preferably 8:1 to 1:2, most preferably 6:1 to 1:1. The gas mixtureand plasma may also include other gasses, such as He, Ne or Ar. Thepressure during etching is greater than 4 mTorr, preferably at least 10mTorr, such as 10-80 mTorr, more preferably at least 15 mtorr, such as15-45 mTorr, most preferably 25-35 mtorr.

[0027] The line-edge roughness achieved is at most 9 nm, preferably atmost 8 nm, more preferably at most 6 nm. Another advantage of thisplasma etching is that it also consumes less photoresist. This plasmaetching may be used in other steps that pattern a nitride layer, forexample, during formation of isolation regions, such as in shallowtrench isolation (STI) processes.

[0028] Referring to FIG. 8, the patterned etch-stop layer may be used asa hard mask for the etching of the metallic layer 125 (FIG. 7) to form apatterned metallic layer 130. Referring to FIG. 9, the patternedetch-stop layer and the patterned metallic layer may be used as a hardmask for the etching of the gate layer 105 (FIG. 8) to form patternedgate layer 110. The gate etching may be carried out by conventional gateetch techniques, for example by exposure to a plasma formed fromchlorine, hydrobromic acid and/or oxygen.

[0029] The patterned photoresist 210 (FIG. 6) may be removed at anystage of the gate stack formation following the etch-stop etch. Forexample, the patterned photoresist may be removed immediately after theetch-stop etch (as illustrated in FIGS. 6 and 7), or it may be removedafter the etching of the metallic layer or after the gate etching. Theremoval of the photoresist may be followed by a cleaning procedure toensure removal of any residual byproduct of the photoresist or of thephotoresist removal. For example, the photoresist may be removed byashing the patterned photoresist to provide a gate stack containing apatterned etch-stop layer (FIG. 7). This gate stack without aphotoresist layer may then be treated with a cleaning solution tocomplete the removal and cleaning process. The most preferred cleaningagent contains water, 2-(2 aminoethoxy) ethanol, hydroxylamine, andcatechol. An example of a cleaning solution is EKC265™ (EKC, Hayward,Calif.).

[0030]FIG. 9 thus illustrates a gate stack 200 which may be formed on asemiconductor wafer. Semiconductor substrate 100 supports a gateinsulating layer 102, which in turn supports a gate layer 110. The gatelayer supports a metallic layer 130, which may optionally be separatedfrom the gate layer by barrier layer 120. The metallic layer mayoptionally support a barrier layer 140. The etch-stop layer 150 is onthe metallic layer 130, or optionally on the layer 140 above themetallic layer.

[0031] Further processing of the gate structure may include formingsidewall oxide regions 170 on gate layer 110 and forming spacers 160(preferably containing nitride) on the sides of the stack. Furthermore,a dielectric layer 180 maybe formed on the etch-stop layer, and contactsor via 190 formed through the dielectric to the substrate, asillustrated in FIG. 10. This via may be lined and filled to form avia-contact, for example with TiN and tungsten, respectively. Otherprocessing may include forming contacts to the gate itself. Afterdielectric layer is formed, the etch-stop layer has a thickness of atleast 800 angstroms, preferably at least 1100 angstroms, so that it maybe used to allow formation of SAC.

[0032] Other processing may be used to complete formation ofsemiconductor devices from the semiconductor structure. For example,source/drain regions 12, 14 may be formed in the substrate, additionaldielectric layers may be formed on the substrate, and contacts andmetallization layers may be formed on these structures. These additionalelements may be formed before, during, or after formation of the gatestack.

[0033] The related processing steps, including the etching of the gatestack layers and other steps such as polishing, cleaning, and depositionsteps, for use in the present invention are well known to those ofordinary skill in the art, and are also described in Encyclopedia ofChemical Technology, Kirk-Othmer, Volume 14, pp. 677-709 (1995);Semiconductor Device Fundamentals, Robert F. Pierret, Addison-Wesley,1996; Wolf, Silicon Processing for the VLSI Era, Lattice Press, 1986,1990, 1995 (vols 1-3, respectively), and Microchip Fabrication 4rd.edition, Peter Van Zant, McGraw-Hill, 2000.

[0034] The semiconductor structures of the present invention may beincorporated into a semiconductor device such as an integrated circuit,for example a memory cell such as an SRAM, a DRAM, an EPROM, an EEPROMetc.; a programmable logic device; a data communications device; a clockgeneration device; etc. Furthermore, any of these semiconductor devicesmay be incorporated in an electronic device, for example a computer, anairplane or an automobile.

EXAMPLE Example 1 Formation of a Gate Structure

[0035] The following detailed steps were used to form the gate stackhaving a split gate: Nitrogen-containing gate oxide formation Polydeposition-single amorphous gate deposit Mask for P-doping P⁺ polyimplantation N-well implantation P-channel implantation P⁺ polyimplantation strip resist Mask for N-doping P-well implantation N⁺ polyimplantation N-channel implantation N⁺ poly implantation strip resistTungsten gate pre-clean Tungsten PVD, sputtering (nitrogen + argon, thenargon only) Nitride-PECVD Deposit ARC and Resist Etch mask for nitrideNitride etch-ARC, silicon nitride, and partial tungsten etch Removeresist Tungsten and Poly etch Post-poly etch clean Selective oxidationN⁺ source/drain extension implant Stripping & cleaning P⁺ source/drainextension implant Stripping & cleaning Nitride spacer deposition (BTBASchemistry) Spacer etch Post-spacer etch clean N⁺ source/drain implantStripping & cleaning P⁺ source/drain implant Stripping & cleaningNitride-poly cut mask etch and clean Dielectricdeposition/planarization/mask for contacts self-aligned contact (SAC)etch SAC etch clean

[0036] Bottom anti-reflective coating (BARC) was etched under thefollowing conditions: CF₄ flow rate of 100 sccm, Ar flow rate of 100sccm, power of 600 W, bias of 75 W, a pressure of 16 mtorr, and atemperature of 60° C. Temperature is controlled, for example, by Hebackside cooling during the BARC etch, as well as in subsequent steps.

[0037] The resist was then trimmed under the following conditions: HBrflow rate of 160 sccm, O₂ flow rate of 28 sccm, power of 400 W, apressure of 8 mtorr, a temperature of 60° C., and for a time of 10seconds. Alternatively, the resist was trimmed under the followingconditions: HBr flow rate of 169 sccm, O₂ flow rate of 19 sccm, power of400 W, a pressure of 8 mTorr, a temperature of 60° C., and for a time of5 seconds.

[0038] Etching of the nitride was carried out with a plasma at apressure of 30 mtorr, at a power of 500 W, a bias of 100 W, and at atemperature of 60-65° C. The gas composition is CHF₃ at 275 sccm and CF₄at 300 sccm. An overetch of 20% was used.

[0039] The tungsten was partially etched under the following conditions:NF₃ flow rate of 10 sccm, Cl₂ flow rate of 25 sccm, O₂ flow rate of 5sccm, Ar flow rate of 50 sccm, N₂ flow rate of 30 sccm, He flow rate of150 sccm, power of 800 W, bias of 60 W, a pressure of 4 mTorr, atemperature of 60° C., and for a time of 10 seconds.

[0040] Resist material was removed by ashing (for example at 80° C. witha mixture of CF₄ and O₂), and the stack was cleaned by treating thewafer with EKC265™ (EKC, Hayward, Calif.; a mixture of 2-(2 aminoethoxy)ethanol, hydroxylamine and catechol) by spinning with spraying (using aspray tool) at 65 or 70° C. for 10 minutes, then 2 minutes at 20° C.,followed by rinsing with deionized water, to prevent undesirableoxidation of the tungsten. This clean may be used for any stripping andcleaning step where tungsten or tungsten nitride is exposed to preventundesirable oxidation. Also, the clean may be carried out withdownstream plasma ashing under the following conditions, followed bywashing with water: step 1: CF₄ flow rate of 50 sccm, H₂O flow rate of160 sccm, N₂/H₂ flow rate of 1400 sccm, power of 1050 W, bias of 100 W,a pressure of 750 mTorr, a temperature of 80° C., and for a time of 30seconds; step 2: NF₃ flow rate of 40 sccm, H₂O flow rate of 170 sccm, O₂flow rate of 170 sccm, bias of 150 W, a pressure of 250 mtorr, atemperature of 80° C., and for a time of 120 seconds.

[0041] The tungsten was then etched under the following conditions: NF₃flow rate of 15 sccm, Cl₂ flow rate of 25 sccm, O₂ flow rate of 5 sccm,Ar flow rate of 50 sccm, N₂ flow rate of 30 sccm, He flow rate of 150sccm, power of 800 W, bias of 35 W, a pressure of 4 mtorr, and atemperature of 60° C. An overetch of the tungsten was carried out for 5seconds. The system was then pumped down for 20 seconds.

[0042] The poly was then etched under the following conditions: HBr flowrate of 250 sccm, He(80%)/O₂(20%) flow rate of 12 sccm, power of 450 W,a bias of 40 W, a pressure of 25 mTorr, and a temperature of 60° C. Apoly overetch was carried out under the following conditions: HBr flowrate of 150 sccm, He(80%)/O₂(20%) flow rate of 8 sccm, He flow rate of100 sccm, power of 200W, a bias of 70W, a pressure of 70 mTorr, atemperature of 60° C., and for a time of 63 seconds. Alternatively, thepoly overetch was carried out under the following conditions: HBr flowrate of 150 sccm, He(80%)/O₂(20%) flow rate of 13 sccm, He flow rate of200 sccm, power of 250 W, a bias of 60 W, a pressure of 80 mTorr, atemperature of 60° C., and for a time of 53 seconds. Cleaning may becarried out as described above, or for example, by downstream, followedby rinsing with water (for example with deionized water for 7 cycles),under the following conditions: CF₄ flow rate of 40 sccm, O₂ flow rateof 1000 sccm, H₂O flow rate of 200 sccm, N₂ flow rate of 150 sccm, powerof 1700 W, a pressure of 700 mTorr, a temperature of 70° C., and for atime of 80 seconds.

[0043] The exposed sides of the poly were covered with a layer of oxideabout 50-70 angstroms thick by the selective oxidation. This was carriedout by exposing the stack to a mixture of hydrogen and oxygen (10%steam) at a temperature of 750° C. to selectively oxidize the polyrelative to the tungsten and tungsten nitride.

[0044] BTBAS was used to form a nitride layer for spacer formation underthe following conditions: BTBAS flow rate of 50 sccm, NH₃ flow rate of100 sccm, a pressure of 150 mTorr, and a temperature of 550° C.

[0045] Etching of the nitride (nitride-poly cut mask etch and clean) wascarried out with a plasma at a pressure of 35 mT, at a power of 280 W,and a temperature of 15° C. The gas composition for the main etch wasCHF₃ at 30 sccm, Ar at 60 sccm, and O₂ at 10 sccm. The clean was carriedout with plasma ashing in two steps, followed by a solvent clean:

[0046] Step 1:

[0047] pressure of 2 mtorr, temperature of 185° C., microwave power of800 W, gas: O₂ at 3750 sccm, N₂ at 375 sccm;

[0048] Step 2:

[0049] same values, except a temperature of 200° C. and microwave powerof 1400 W.

[0050] Etching to form contacts (SAC etch) was carried out with a plasmaat a pressure of 55 mTorr, a power of 500 W, a temperature of 35° C.,with the magnet at 20 Gauss, a gas of CF₄ at 5 sccm, CHF₃ at 10 sccm,C₂H₂F₄ at 10 sccm, and Ar at 90 sccm, as the ARC etch; and as the mainetch a pressure of 55 mtorr, a power of 500 W, a tempature of 35° C.,with the magnet at 25 Gauss, a gas of CHF₃ at 80 sccm, C₂H₂F₄ at 8 sccm,and Ar at 90 sccm. The clean was carried out with plasma ashing in twosteps, followed by a solvent clean:

[0051] Step 1:

[0052] pressure of 400 mTorr, temperature of 20+/−5° C., RF power of 420W, gas: O₂ at 400 sccm.

[0053] Step 2:

[0054] pressure of 750 mTorr, temperature of 20+/−5° C., RF power of 420W, gas: N₂ at 400 sccm, H₂ at 400 sccm, and NF₃ at 5 sccm; oralternatively:

[0055] pressure of 750 mTorr, temperature of 40+/−5° C., RF power of 350W, gas: CF₄ at 20 sccm, N₂/5% H₂ at 200 sccm, and O₂ at 500 sccm.

[0056] SAC etch clean was carried out using EKC265™, with a spray tool:temperature of 70° C. for 10 minutes, and an extra 2 minutes at 20° C.,followed by rinsing with deionized water and then spin drying in N₂;then washed with H₂SO₄ at 150° C. twice for 10 minutes each and thenspin drying in N₂.

[0057] In the stack, the silicon nitride layer had a thickness of 1300angstroms (although the actual amount deposited was greater sincesilicon nitride is lost during the poly etch and during spacer etch),the tungsten layer had a thickness of 325 angstroms, the tungstennitride layer had a thickness of 75 angstroms, and the poly layer had athickness of 735 angstroms. The contacts having a width of 0.13 micronsat the top, and a width of 0.05 microns at the bottom.

1. A method of making a semiconductor structure, comprising: etching anitride layer with a plasma to form a patterned nitride layer, whereinthe nitride layer is on a semiconductor substrate, a photoresist layeris on the nitride layer, and the plasma is prepared from a gas mixturecomprising CF₄ and CHF₃ at a pressure of at least 10 mTorr.
 2. Themethod of claim 1, wherein the gas mixture comprises a ratio of CF₄:CHF₃ of 10:1 to 1:3.
 3. The method of claim 1, wherein the pressure is15-45 mTorr.
 4. The method of claim 1, wherein the photoresist layercomprises 193 nm photoresist.
 5. The method of claim 1, wherein thepatterned nitride layer has a line-edge roughness of at most 9 nm. 6.The method of claim 1, wherein the gas mixture comprises a ratio ofCF₄:CHF₃ of 8:1 to 1:2, the pressure is 25-35 mTorr, and the photoresistlayer comprises 193 nm photoresist.
 7. A method of making asemiconductor structure, comprising: etching a nitride layer with aplasma to form a patterned nitride layer, wherein the nitride layer ison a stack, the stack is on a semiconductor substrate, the stackcomprises (i) a gate layer, comprising silicon, and (ii) a metalliclayer, on the gate layer, a photoresist layer is on the nitride layer,the photoresist layer comprises a 193 nm photoresist, the patternednitride layer has a line-edge roughness of at most 8 nm, and the plasmacomprises carbon, hydrogen and fluorine.
 8. The method of claim 7,wherein the patterned nitride layer has a line-edge roughness of at most6 nm.
 9. The method of claim 7, wherein the plasma is prepared from agas mixture at a pressure of at least 15 mtorr.
 10. The method of claim7, wherein the plasma is prepared from a gas mixture at a pressure of25-35 mTorr.
 11. The method of claim 7, wherein the gate layer comprisesa P⁺ region and an N⁺ region, and wherein the P⁺ and N⁺ regions areseparated by a region which is on an isolation region of the substratehaving a width of at most 0.4 microns.
 12. A method of making asemiconductor device, comprising: forming a semiconductor structure bythe method of claim 1, and forming a semiconductor device from thesemiconductor structure.
 13. A method of making an electronic device,comprising: forming a semiconductor device by the method of claim 12,and forming an electronic device comprising the semiconductor device.14. A method of making a semiconductor device, comprising: forming asemiconductor structure by the method of claim 7, and forming asemiconductor device from the semiconductor structure.
 15. A method ofmaking an electronic device, comprising: forming a semiconductor deviceby the method of claim 14, and forming an electronic device comprisingthe semiconductor device.
 16. A semiconductor structure produced by themethod of claim
 1. 17. A semiconductor structure produced by the methodof claim
 7. 18. A semiconductor structure, comprising: A patternednitride layer on a semiconductor substrate, wherein the patternednitride layer has a line-edge roughness of at most 9 nm, and anisolation region of the substrate has a width of at most 0.4 microns.19. The semiconductor structure of claim 18, further comprising a stack,between the nitride layer and the semiconductor substrate, wherein thestack comprises (i) a gate layer, comprising silicon, and (ii) ametallic layer, on the gate layer, and the gate layer is on theisolation.
 20. The semiconductor structure of claim 18, wherein thepatterned nitride layer has a line-edge roughness of at most 6 nm.